The trend in the semiconductor manufacturing industry is to use copper metal as interconnect material in so-called damascene or dual damascene processes. Damascene is an interconnection fabrication process in which grooves or trenches are formed in an insulating layer and then filled with metal to form the conductive lines that interconnect the component parts of an integrated circuit. Dual damascene is a multi-level interconnect process in which via openings are formed in addition to forming the trenches of the single damascene process. A two-tiered opening is formed at locations where the vias extend downward from the groove or trench. Interconnect lines are then formed by introducing conductive material into the dual damascene openings. These conductive lines interconnect active and passive elements of the integrated circuit formed on the semiconductor substrate.
Another trend in the semiconductor manufacturing industry is the use of low-k dielectric materials, particularly as inter-metal dielectrics (IMDs). A low-k dielectric material is defined as a dielectric material having a dielectric constant, k, less than that of SiO2, which has a dielectric constant of about 4. There are generally two types of low-k dielectric materials for semiconductor fabrication processes: modified SiO2 materials; and, organic materials such as polyimides and other polymers. Low-k dielectric materials include such commercial products as Dow Corning's SiLK™ and porous SiLK™, Applied Materials' Black Diamond™, Texas Instruments'Coral™ and other organic polymers, porous oxides and carbon-doped oxides. The electrical characteristics of low-k dielectric materials generally make them desirable in the manufacture of semiconductor chips having sub-micron features because the capacitive effects between closely-spaced electrical conductors is diminished. Such conductors include, for example, dual damascene-formed copper conductors used to make back-end-of-line (BEOL) multilevel electrical connections to silicon devices such as transistors. Therefore, in one particular application of interest, low-k dielectric materials may be used to insulate sub-micron, dual damascene copper interconnects from one another.
When a single low-k dielectric material is used as the IMD in which a two-tiered, dual-damascene opening is to be formed, however, it is difficult to accurately terminate the etch process used to form the upper portion of the dual-damascene opening called the groove or trench. The trench etching process must be terminated based on etching time. If the trench etching process is terminated too early or the IMD layer is too thick, a short upper portion and a via with an undesirably high aspect ratio may result. If the trench etching process is terminated too late or the IMD layer is too thick, the trench may extend through the entire dielectric layer obliterating the via and producing a single damascene structure. As such, non-uniformities of the IMD low-k dielectric material as well as non-uniformities of the etching process itself, render it difficult to form correctly proportioned dual-damascene openings across the substrate without an endpointing system that is available to accurately terminate the etching process based on a physical or chemical change.
Furthermore, each particular low-k dielectric material typically provides a particularly advantageous electrical transport or mechanical quality, often to the exclusion of another. For example, low-k dielectric materials formed using CVD (chemical vapor deposition) such as commonly used to form modified SiO2 low-k dielectric materials, generally provide good mechanical characteristics but somewhat less-than-optimum electrical characteristics. Conversely, low-k dielectric materials formed using a spin-on process, such as organic low-k dielectric materials, typically provide superior electrical transport properties at the expense of strong mechanical properties.
It would therefore be desirable to provide a dual-damascene structure formed in an intermetal dielectric layer that incorporates both the desirable mechanical properties and electrical transport properties available in various low-k materials. It would further be desirable to form the dual damascene structure using a process that can be reliably endpointed to produce an accurately proportioned dual-damascene structure uniformly throughout the semiconductor devices being fabricated on the substrate.